HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 93

• Manufacturer Part Number: HD64F3644H
• Description: IC H8 MCU FLASH 32K 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.3.3
There are 12 external interrupts: IRQ
Interrupts IRQ
IRQ
depending on the settings of bits IEG3 to IEG0 in IEGR1.
When these pins are designated as pins IRQ
edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of
these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1.
These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ
numbers 7 to 4 are assigned to interrupts IRQ
to IRQ
INT Interrupts: INT interrupts are requested by input signals to pins INT
interrupts are detected by either rising edge sensing or falling edge sensing, depending on the
settings of bits INTEG7 to INTEG0 in IEGR2.
When the designated edge is input at pins INT
requesting an interrupt. Recognition of these interrupt requests can be disabled individually by
clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the
I bit to 1 in CCR.
When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is
assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupt-
handling routine must discriminate the interrupt source.
Note: Pins INT
0
. These interrupts are detected by either rising edge sensing or falling edge sensing,
3
the designated edge is input or output, the corresponding bit INTFn is set to 1.
(low). Table 3.2 gives details.
External Interrupts
3
to IRQ
3
7
to IRQ
to INT
0
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
0
0
: Interrupts IRQ
are multiplexed with port 5. Even in port usage of these pins, whenever
3
to IRQ
3
to IRQ
3
to IRQ
0
3
7
and INT
to IRQ
to INT
0
are requested by input signals to pins IRQ
0
in port mode register 1 and the designated
0
0
. The order of priority is from IRQ
7
, the corresponding bit in IRR3 is set to 1,
to INT
Rev. 6.00 Sep 12, 2006 page 71 of 526
0
.
Section 3 Exception Handling
7
to INT
REJ09B0326-0600
0
. These
0
(high)
3
to