D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 214
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller
6.7.5
Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a
transition is made to sleep mode when either of these settings has been made.
6.8
6.8.1
The chip has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal.
The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means
of a bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.8.2
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
An internal bus access by an internal bus master and external bus release, can be executed in
parallel.
In the event of simultaneous external bus release request and internal bus master external access
request generation, the order of priority is as follows:
Rev.7.00 Feb. 14, 2007 page 180 of 1108
REJ09B0089-0700
Usage Note
Bus Arbitration
Overview
Operation
(High) DTC > CPU (Low)
(High) External bus release > Internal bus master external access (Low)
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