D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 289
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Mode 7 *
Note: * Modes 6 and 7 are not available in the ROMless versions.
Port A Data Register (PADR)
Bit
Initial value : Undefined Undefined Undefined Undefined
R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port A Register (PORTA)
Bit
Initial value : Undefined Undefined Undefined Undefined
R/W
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
Setting PADDR bits to 1 makes the corresponding port A pins output ports, while clearing the
bits to 0 makes the pins input ports.
:
:
:
:
—
—
—
—
7
7
—
—
—
—
6
6
—
—
—
—
5
5
—
—
—
—
4
4
Rev.7.00 Feb. 14, 2007 page 255 of 1108
PA3DR
R/W
PA3
— *
R
3
0
3
PA2DR
R/W
PA2
— *
R
2
0
2
Section 8 I/O Ports
PA1DR
REJ09B0089-0700
R/W
PA1
— *
R
1
0
1
PA0DR
R/W
PA0
— *
R
0
0
0
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