D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 364
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.2.4
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset and in hardware standby mode.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE
0
1
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Rev.7.00 Feb. 14, 2007 page 330 of 1108
REJ09B0089-0700
Channel 0: TIER0
Channel 3: TIER3
Bit
Initial value :
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
Initial value :
R/W
Timer Interrupt Enable Registers (TIER)
Description
A/D conversion start request generation disabled
A/D conversion start request generation enabled
:
:
:
:
TTGE
TTGE
R/W
R/W
7
0
7
0
—
—
—
—
6
1
6
1
TCIEU
R/W
—
—
5
0
5
0
TCIEV
TCIEV
R/W
R/W
4
0
4
0
TGIED
R/W
—
—
3
0
3
0
TGIEC
R/W
—
—
2
0
2
0
TGIEB
TGIEB
R/W
R/W
1
0
1
0
(Initial value)
TGIEA
TGIEA
R/W
R/W
0
0
0
0
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