HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 210
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Figure 6.25 shows the timing for transition to the bus-released state.
6.9.1
When MSTPCR is set to H'FFFFFF and transmitted to sleep mode, the external bus release does
not function. To activate the external bus release in sleep mode, do not set MSTPCR to H'FFFFFF.
Rev.7.00 Dec. 24, 2008 Page 154 of 698
REJ09B0074-0700
Address bus
HWR, LWR
Data bus
Bus Release Usage Note
Note : n = 0 to 5
[1]
[2]
[3]
[4]
[5]
BREQ
BACK
CSn
RD
AS
φ
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus
master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Figure 6.25 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
[3]
state.
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
CPU
cycle
[5]
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