HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 245
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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7.4.6
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in
response to a single transfer request, and this is executed the specified number of times. The
transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer
source or the transfer destination can be selected as a block area (an area composed of a number of
bytes or words). Table 7.7 summarizes register functions in block transfer mode.
Table 7.7
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Register
23
23
15
7
7
ETCRAH
Block Transfer Mode
ETCRAL
ETCRB
MARA
MARB
Register Functions in Block Transfer Mode
0
0
0
0
0
Function
Source address
register
Description address
register
Holds block size
Block size counter
Block transfer
counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Block size
Number of block
transfers
Block size
Rev.7.00 Dec. 24, 2008 Page 189 of 698
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
decremented every
transfer; ETCRH value
copied when count reaches
H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
REJ09B0074-0700
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