HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 534
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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14.3.10 USB Endpoint Data Register 0o (UEDR0o)
UEDR0o is a data register for endpoint 0 (for Control_out transfer). UEDR0o stores data received
from the host. The number of data items to be read must be the number of bytes specified by
UESZ0o.
When 1 byte is read from UEDR0o, UESZ0o is decremented by1.
UEDR0o is a byte register to which 4-byte address area is assigned. Accordingly, UEDR0o allows
the user to read 2-byte or 4-byte data continuously by word transfer or longword transfer.
14.3.11 USB Endpoint Data Register 3 (UEDR3)
UEDR3 is a data register for endpoint 3 (for Interrupt_in transfer). UEDR3 stores data to be sent to
the host. The number of data items to be written continuously must be the maximum packet size or
less.
UEDR3 is a byte register to which 4-byte address area is assigned. Accordingly, UEDR3 allows
the user to write 2-byte or 4-byte data continuously by word transfer or longword transfer. For
details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
14.3.12 USB Endpoint Data Register 1 (UEDR1)
UEDR1 is a data register for endpoint 1 (for Bulk_in transfer). UEDR1 stores data to be sent to the
host. The number of data items to be written continuously must be the maximum packet size or
less.
UEDR1 is a byte register to which 4-byte address area is assigned. Accordingly, UEDR1 allows
the user to write 2-byte or 4-byte data continuously by word transfer or longword transfer. For
details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Rev.7.00 Dec. 24, 2008 Page 478 of 698
REJ09B0074-0700
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit Name
Bit Name
Bit Name
Initial Value R/W
—
Initial Value R/W
All 0
Initial Value R/W
All 0
R
W
W
Description
These bits store data for Control_out transfer
Description
These bits store data for Interrupt_in transfer
Description
These bits store data for Bulk_in transfer
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