HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 619
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 619 of 758
- Download datasheet (5Mb)
Note: * Set according to the FWE pin state.
17.5.2
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit
2
1
0
Bit
7
6 to 0 —
Bit Name Initial Value
PV1
E1
P1
Bit Name Initial Value
FLER
Flash Memory Control Register 2 (FLMCR2)
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
—
Description
Program-Verify
When this bit is set to 1, the flash memory transits to
program-verify mode. When it is cleared to 0, program-
verify mode is cancelled.
[Setting condition]
When FWE = 1 and SWE1 = 1
Erase
When this bit is set to 1 while the SWE1 and ESU1 bits
are 1, the flash memory transits to erase mode. When it
is cleared to 0, erase mode is cancelled.
[Setting condition]
When FWE = 1, SWE1 = 1, and ESU1 = 1
Program
When this bit is set to 1 while the SWE1 and PSU1 bits
are 1, the flash memory transits to program mode.
When it is cleared to 0, program mode is cancelled.
[Setting condition]
When FWE = 1, SWE1 = 1, and PSU1 = 1
Description
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When
FLER is set to 1, flash memory goes to the error-
protection state.
See section 17.9.3, Error Protection, for details.
Reserved
These bits are always read as 0.
Rev.7.00 Dec. 24, 2008 Page 563 of 698
REJ09B0074-0700
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