HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 373
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
HD64F3644WV
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Bit 7 A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7: ADSF
0
1
Bits 6 to 0 Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be
modified.
12.3
12.3.1
The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit TRGE in AMR is set to 1. Then when
the input signal edge designated in bit INTEG5 of interrupt edge select register 2 (IEGR2) is
detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion.
Figure 12.2 shows the timing.
A/D Conversion Operation
Operation
Start of A/D Conversion by External Trigger Input
Read: Indicates the completion of A/D conversion
Write: Stops A/D conversion
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Description
Rev. 6.00 Sep 12, 2006 page 351 of 526
Section 12 A/D Converter
REJ09B0326-0600
(initial value)
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