R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 239
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
6.6.3
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access
space, AD15 to AD8 are valid for both address and data. For the 16-bit access space, AD15 to
AD0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the
corresponding address will be output to the address bus. For details on access size and data
alignment, see section 6.5.1, Data Size and Data Alignment.
6.6.4
In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching
the address is output. The AH output pin is multiplexed with the AS output pin. When the external
address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions
as the AH output pin. Note however that the multiplexed pin will function as the AS output pin
until the address/data multiplexed I/O space is specified.
6.6.5
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR,
WTCRAH, RDNCR, and CSACR.
(1)
Figure 6.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access
space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used.
Wait states cannot be inserted in the data cycle.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
8-Bit, 2-State Data Access Space
Data Bus
Address Hold Signal
Basic Timing
Section 6 Bus Controller (BSC)
Page 209 of 1372
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