M30626SPFP#U5C Renesas Electronics America, M30626SPFP#U5C Datasheet - Page 132

IC M16C/62P MCU ROMLESS 100QFP

M30626SPFP#U5C

Manufacturer Part Number
M30626SPFP#U5C
Description
IC M16C/62P MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626SPFP#U5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30626SPFP#U5CM30626SPFP#U3C
Manufacturer:
TOSHIBA
Quantity:
101
Company:
Part Number:
M30626SPFP#U5CM30626SPFP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30626SPFP#U5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.6
12.5.5
12.5.6
Table 12.5
Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection,
Low Voltage Detection
Software, Address Match, DBC, Single-Step
Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a
time from when an interrupt request is generated till when the first instruction in the interrupt routine is
executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction
then executing is completed ((a) on Figure 12.6) and a time during which the interrupt sequence is executed ((b)
on Figure 12.6).
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the
IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in
Table 12.5 is set in the IPL. Table 12.5 lists the IPL Level That is Set to IPL When a Software or Special
Interrupt is Accepted.
Jan 10, 2006
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
(b) A time during which the interrupt sequence is executed. For details, see the table
Interrupt Response Time
Variation of IPL when Interrupt Request is Accepted
Interrupt Vector Address
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Response Time
IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted
Even
Even
Odd
Odd
Instruction
Page 115 of 390
Interrupt Sources
(a)
Interrupt response time
Interrupt request acknowledged
SP Value 16-Bit Bus, Without Wait
Even
Even
Odd
Odd
Interrupt sequence
(b)
18 cycles
19 cycles
19 cycles
20 cycles
7
Not changed
interrupt routine
Instruction in
8-Bit Bus, Without Wait
Level that is Set to IPL
20 cycles
20 cycles
20 cycles
20 cycles
Time
12. Interrupt

Related parts for M30626SPFP#U5C