M30626SPFP#U5C Renesas Electronics America, M30626SPFP#U5C Datasheet - Page 137

• Manufacturer Part Number: M30626SPFP#U5C
• Description: IC M16C/62P MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
12.6
Figure 12.11
Interrupt Factor Select Register 2
Interrupt Factor Select Register
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi
bit in the IFSR register.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use
the INT4 interrupt, set the IFSR6 bit in the IFSR register to “1” (= INT4). To use the INT5 interrupt, set the IFSR7
bit in the IFSR register to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
Figure 12.11 shows the IFSR and IFSR2A Registers.
b7 b6 b5 b4
NOTES :
b7 b6 b5 b4
NOTES :
1.
2.
1.
2.
3. When setting this bit to “0” (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC registers are set to “0”
Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer B3
interrupt, clear the IFSR26 bit to “0” (Timer B3). When using UART0 bus collision detection, set the IFSR26 bit to “1”.
Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using Timer B4
interrupt, clear the IFSR27 bit to “0” (Timer B4). When using UART1 bus collision detection, set the IFSR27 bit to “1”.
When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register are set to “0”
During memory expansion and microprocessor modes, w hen the data bus is 16 bits w ide (BYTE pin is "L"), set
this bit to “0” (= SI/O3, SI/O4).
INT Interrupt
(= falling edge).
(= falling edge).
Jan 10, 2006
b3 b2
b3 b2 b1 b0
b1
IFSR and IFSR2A Registers
b0
Bit Symbol
Bit Symbol
IFSR2A
(b5-b0)
Symbol
IFSR26
IFSR27
Symbol
IFSR0
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
IFSR
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Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Interrupt Request Factor Select Bit
Interrupt Request Factor Select Bit
INT0 Interrupt Polarity Sw itching Bit
INT1 Interrupt Polarity Sw itching Bit
INT2 Interrupt Polarity Sw itching Bit
INT3 Interrupt Polarity Sw itching Bit
INT4 Interrupt Polarity Sw itching Bit
INT5 Interrupt Polarity Sw itching Bit
Interrupt Request Factor Select Bit
Interrupt Request Factor Select Bit
Address
Bit Name
Address
Bit Name
035Eh
035Fh
(1)
(2)
(2)
(2)
0 : Timer B3
1 : UART0 bus collision detection
0 : Timer B4
1 : UART1 bus collision detection
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
_____
_____
(3)
(3)
00XXXXXXb
After Reset
(1)
(1)
(1)
(1)
(1)
(1)
After Reset
Function
Function
00h
12. Interrupt
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—