M30626SPFP#U5C Renesas Electronics America, M30626SPFP#U5C Datasheet - Page 141

• Manufacturer Part Number: M30626SPFP#U5C
• Description: IC M16C/62P MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
13. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using
the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts
down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt
request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after
reaching the terminal count can be selected using the PM12 bit of PM1 register. The PM12 bit can only be set to “1”
(reset). Once this bit is set to “1,” it cannot be set to “0” (watchdog timer interrupt) in a program. Refer to 5.4
Watchdog Timer Reset for the details of watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the divide-by-N value for
the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide by- N value for the
prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given
below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock chosen for CPU clock, on-chip oscillator clock, PLL clock
With sub-clock chosen for CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period
is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the
watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting
by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the
held value when the modes or state are released.
Figure 13.1 shows the Watchdog Timer Block Diagram. Figure 13.2 shows the WDC and WDTS Register.
Figure 13.1
Watchdog timer period
Watchdog timer period
HOLD
CPU
clock
CM07: Bit in CM0 register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
PM22: Bit in PM2 register
Write to WDTS register
Internal RESET signal
(“L” active)
Jan 10, 2006
Watchdog Timer Block Diagram
On-chip oscillator clock
Page 124 of 390
Prescaler
1/128
1/16
1/2
=
=
CM07 = 0
WDC7 = 0
CM07 = 0
WDC7 = 1
CM07 = 1
Prescaler dividing (16 or 128) × Watchdog timer count (32768)
Prescaler dividing (2) × Watchdog timer count (32768)
PM22 = 1
PM22 = 0
CPU clock
CPU clock
Watchdog timer
Set to
“7FFFh”
PM12 = 0
PM12 = 1
13. Watchdog Timer
Reset
Watchdog timer
interrupt request