M30626SPFP#U5C Renesas Electronics America, M30626SPFP#U5C Datasheet - Page 152

• Manufacturer Part Number: M30626SPFP#U5C
• Description: IC M16C/62P MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
14.3
14.4
Table 14.4
DMA Factor
Software Trigger
Peripheral Function
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However, if a
DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
If the DMAi is not in an initial state, the above steps should be repeated.
The DMAC can generate a DMA request as triggered by the factor of request that is selected with the DMS and
DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 14.4 lists the Timing at Which the
DMAS Bit Changes State.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether or not
the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set to “0”
(DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a program (it can
only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be
sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the DMAS bit
in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the DMAC is enabled.
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
DMA Enable
DMA Request
Jan 10, 2006
is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
Timing at Which the DMAS Bit Changes State
When the DSR bit in the DMiSL register
is set to “1”
When the interrupt control register for
the peripheral function that is selected
by the DSEL3 to DSEL0 and DMS bits
in the DMiSL register has its IR bit set
to “1”
Page 135 of 390
Timing at which the bit is set to “1”
DMAS Bit of the DMiCON Register
• Immediately before a data transfer starts
• When set by writing “0” in a program
Timing at which the bit is set to “0”
14. DMAC