M30626SPFP#U5C Renesas Electronics America, M30626SPFP#U5C Datasheet - Page 74

• Manufacturer Part Number: M30626SPFP#U5C
• Description: IC M16C/62P MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPFP#U5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 7.2
Processor Mode Register 1
b7 b6 b5 b4
NOTES :
0
1.
2.
3.
4.
5.
6.
7.
Internal
Access Area
Jan 10, 2006
Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
Set the PM10 bit to “0” for Mask ROM version. For flash memory version, the PM10 bit controls w hether Block A is
enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
In addition, the PM10 bit is automatically set to “1” w hile the FMR01 bit in the FMR0 register is set to “1” (CPU
rew rite mode).
Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor
mode).
PM12 bit is set to “1” by w riting a “1” in a program (w riting a “0” has no effect).
When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or
internal ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0”
(w ith w ait state).
The PM13 bit is automatically set to “1” w hen the FMR01 bit in the FMR0 register is “1” (CPU rew rite mode).
The access area is changed by the PM13 bit as listed in the table below .
External
b3 b2 b1 b0
RAM
ROM
PM1 Register
Up to Addresses 00400h to 03FFFh (15 Kbytes)
Up to Addresses D0000h to FFFFFh (192 Kbytes)
Address 04000h to 07FFFh are usable
Address 80000h to CFFFFh are usable
Bit Symbol
Symbol
PM10
PM11
PM12
PM13
PM14
PM15
PM17
PM1
(b6)
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CS2 Area Sw itch Bit
(Data Block Enable Bit)
Port P3_7 to P3_4 Function Select
Bit
Watchdog Timer Function Select Bit
Internal Reserved Area Expansion
Bit
Memory Area Expansion Bit
Reserved Bit
Wait Bit
(1)
(3)
(6)
(5)
PM13=0
Address
Bit Name
0005h
(2)
(3)
b5 b4
0 0 : 1-Mbyte mode (Do not expand)
0 1 : Do not set
1 0 : Do not set
1 1 : 4-Mbyte mode
0 : 08000h to 26FFFh (Block A disable)
1 : 10000h to 26FFFh (Block A enable)
0 : Address output
1 : Port function
0 : Watchdog timer interrupt
1 : Watchdog timer reset
(NOTE 7)
Set to “0”.
0 : No w ait state
1 : With w ait state (1 w ait)
The entire area is usable
The entire area is usable
Address 04000h to 07FFFh are reserved
Address 80000h to CFFFFh are reserved
(Memory expansion mode)
After Reset
0X001000b
Function
PM13=1
(4)
7. Processor Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW