MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 311

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

M68HC16 Z SERIES
USER’S MANUAL
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specifi-
12. After external RESET negation is detected, a short transition period (approximately 2 t
13. External logic must pull RESET high during this period in order for normal MCU operation to begin.
14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
3. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low dur-
4. Address access time = (2.5 + WS) t
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the
6. If multiple-chip selects are used, CS width negated (specification 15) applies to the time from the negation of
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on
8. Maximum value is equal to (t
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data
of the current operand transfer are complete.
cation 47A).
SIM drives RESET low for 512 t
ing reset) do not pertain to an external reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference
signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
Chip select access time = (2 + WS) t
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS
to fall outside the limits shown in specification 9.
a heavily loaded chip-select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip-selects does not apply to chip selects being used for synchronous ECLK cycles.
fast cycle reads. The user is free to use either hold time.
setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored.
The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle.
BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock
cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
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ELECTRICAL CHARACTERISTICS
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.
Go to: www.freescale.com
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