D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 1178

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TIOR1—Timer I/O Control Register 1
Rev.4.00 Sep. 07, 2007 Page 1146 of 1210
REJ09B0245-0400
Bit
Initial value
Read/Write
:
:
:
TGR1B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
0
1
*
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR1B
is output
compare
register
TGR1B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCB
Capture input
source is TGR0C
compare match/
input capture
IOB0
R/W
TGR1A I/O Control
4
0
1
0
1
pin
0
1
0
1
IOA3
R/W
3
0
0
1
0
1
0
1
*
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0C compare match/input
capture
0
1
0
1
0
1
0
1
0
1
*
*
IOA2
TGR1A
is output
compare
register
TGR1A
is input
capture
register
R/W
2
0
H'FFE2
IOA1
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA
Capture input
source is TGR0A
compare match/
input capture
R/W
1
0
1
* : Don't care
pin
IOA0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
* : Don't care
TPU1