D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 119
D12332VFC20V
Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12332VFC20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Priority
High
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in the program
Overview
Exception Handling Types and Priority
Exception Type
Trace *
Interrupt
Trap instruction (TRAPA) *
Reset
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued *
Started by execution of a trap instruction (TRAPA)
2
Rev.4.00 Sep. 07, 2007 Page 87 of 1210
REJ09B0245-0400
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