D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 264
D12332VFC20V
Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12332VFC20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Bit 4
DTE0
0
1
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an
interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when
DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer
break interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1
transfer break interrupt.
Bit 3
DTIE1B
0
1
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0
transfer break interrupt.
Bit 1
DTIE0B
0
1
Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable
an interrupt to the CPU or DTC when transfer ends. If the DTIEA bit is set to 1 when DTE = 0,
the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt
request to the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Rev.4.00 Sep. 07, 2007 Page 232 of 1210
REJ09B0245-0400
Description
Data transfer disabled
Data transfer enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
(Initial value)
(Initial value)
(Initial value)
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