M30802SGP#U5 Renesas Electronics America, M30802SGP#U5 Datasheet - Page 29

• Manufacturer Part Number: M30802SGP#U5
• Description: IC M16C MCU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802SGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 81
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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E
1
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J
6
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0
C
(17) Flag register (FLG)
9
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B
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3.2 shows the flag
register (FLG). The following explains the function of each flag:
0
0
• Bit 0: Carry flag (C flag)
• Bit 1: Debug flag (D flag)
• Bit 2: Zero flag (Z flag)
• Bit 3: Sign flag (S flag)
• Bit 4: Register bank select flag (B flag)
• Bit 5: Overflow flag (O flag)
• Bit 6: Interrupt enable flag (I flag)
• Bit 7: Stack pointer select flag (U flag)
• Bits 8 to 11: Reserved area
0
1
A
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared
to “0”.
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank
1 is selected when this flag is “1”.
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is
cleared to “0” when the interrupt is acknowledged.
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of
software interrupt Nos. 0 to 31 is executed.
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3. Central Processing Unit (CPU)