HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 117

IC H8/3644 MCU FLASH 32K 64SDIP

HD64F3644PV

Manufacturer Part Number
HD64F3644PV
Description
IC H8/3644 MCU FLASH 32K 64SDIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644PV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644PV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
HD64F3644PV
Manufacturer:
RENESAS
Quantity:
25
5.2.3
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
5.3
5.3.1
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2
Standby mode is cleared by an interrupt (IRQ
Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire
chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in
active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON
= 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.
Clock Frequency in Sleep (Medium-Speed) Mode
Standby Mode
Transition to Standby Mode
Clearing Standby Mode
1
or IRQ
0
) or by input at the RES pin.
Rev. 6.00 Sep 12, 2006 page 95 of 526
Section 5 Power-Down Modes
REJ09B0326-0600

Related parts for HD64F3644PV