HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 246

IC H8/3644 MCU FLASH 32K 64SDIP

HD64F3644PV

Manufacturer Part Number
HD64F3644PV
Description
IC H8/3644 MCU FLASH 32K 64SDIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644PV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644PV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
HD64F3644PV
Manufacturer:
RENESAS
Quantity:
25
Section 9 Timers
9.4.3
Timer Operation
Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0
to H'00, TCSRV to H'10, and TCRV1 to H'E2.
Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock,
as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. The valid edge or edges
of the external clock can also be selected by CKS2 to CKS0. When the clock source is selected,
TCNTV starts counting the selected clock input.
The TCNTV contents are always compared with TCORA and TCORB. When a match occurs, the
CMFA or CMFB bit is set to 1 in TCSRV. If CMIEA or CMIEB is set to 1 in TCRV0, a CPU
interrupt is requested. At the same time, the output level selected by bits OS3 to OS0 in TCSRV is
output from the TMOV pin.
When TCNT overflows from H'FF to H'00, if OVIE is 1 in TCRV0, a CPU interrupt is requested.
If bits CCLR1 and CCLR0 in TCRV0 are set to 01 (clear by compare match A) or 10 (clear by
compare match B), TCNTV is cleared by the corresponding compare match. If these bits are set to
11, TCNTV is cleared by input of a rising edge at the TMRIV pin.
When the counter clear event selected by bits CCLR1 and CCLR0 in TCRV0 occurs, TCNTV is
cleared and the count-up is halted. TCNTV starts counting when the signal edge selected by bits
TVEG1 and TVEG0 in TCRV1 is input at the TRGV pin.
Rev. 6.00 Sep 12, 2006 page 224 of 526
REJ09B0326-0600

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