HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 310

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
TAIL MARK: TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output
waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in the figure is
determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1.
SCK
SO
Transmitting: A transmit operation is carried out as follows.
1. Set bit SOL in SCSR1 to 1.
2. Set bits SO1 and SCK1 to 1 in PMR3 to select the S0
3. Clear bit SNC1 in SCR1 to 0 and set bit SNC0 to 0 or 1, designating 8-bit mode or 16-bit
4. Write transmit data in SDRL and SDRU as follows, and select TAIL MARK with bit LTCH in
5. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin S0
6. After 8- or 16-bit data transmission is complete, bit STF in SCSR1 is cleared to 0 and bit
Data can be sent continuously by repeating steps 4 to 6. Check that SCI1 is in the idle state before
rewriting bit MRKON in SCR1.
Rev. 6.00 Sep 12, 2006 page 288 of 526
REJ09B0326-0600
1
PMR7 to 1 for NMOS open-drain output at pin SO
mode. Set bit MRKON in SCR1 to 1, selecting SSB mode.
SCR1.
8-bit mode: SDRL
16-bit mode: Upper byte in SDRU, lower byte in SDRL
IRRS1 in interrupt request register 2 (IRRS2) is set to 1. The selected TAIL MARK is output
after the data transmission. During TAIL MARK output, bit MTRF in SCSR1 is set to 1.
1
Bit 14
t
t
Bit 15
t
Figure 10.5 HOLD TAIL and LATCH TAIL Waveforms
< HOLD TAIL >
2t
t
t
t
Bit 0
SCK
SO
1
1
1
.
1
Bit 14
and SCK
t
Bit 15
t
t
1
pin functions. Set bit POF1 in
< LATCH TAIL >
2t
t
t
1
.