HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 317

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 6 Character Length (CHR): Bit 6 selects either 7 or 8 bits as the data length to be used in
asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6
setting.
Bit 6: CHR
0
1
Note:
Bit 5 Parity Enable (PE): Bit 5 selects whether a parity bit is to be added during transmission
and checked during reception in asynchronous mode. In synchronous mode parity bit addition and
checking is not performed, irrespective of the bit 5 setting.
Bit 5: PE
0
1
Note:
Bit 4 Parity Mode (PM): Bit 4 selects whether even or odd parity is to be used for parity
addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set
to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode,
and in asynchronous mode if parity bit addition and checking is disabled.
Bit 4: PM
0
1
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
* When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
* When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
2. When odd parity is selected, a parity bit is added in transmission so that the total
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
8-bit data
7-bit data *
Parity bit addition and checking disabled
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
Description
Description
2
1
Section 10 Serial Communication Interface
Rev. 6.00 Sep 12, 2006 page 295 of 526
REJ09B0326-0600
(initial value)
(initial value)
(initial value)