HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 318

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Bit 3 Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous
mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is
selected the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP
0
1
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2 Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication
function. When the multiprocessor communication function is enabled, the parity settings in the
PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When
synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor
communication function, see section 10.3.6, Multiprocessor Communication Function.
Bit 2: MP
0
1
Bits 1 and 0 Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 choose /64, /16, /4, or as the
clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see Bit Rate
Register (BRR).
Bit 1: CKS1
0
1
Rev. 6.00 Sep 12, 2006 page 296 of 526
REJ09B0326-0600
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
Bit 0: CKS0
0
1
0
1
Description
1 stop bit *
2 stop bits *
Description
Multiprocessor communication function disabled
Multiprocessor communication function enabled
1
2
Description
/4 clock
/16 clock
/64 clock
clock
(initial value)
(initial value)
(initial value)