HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 320

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Bit 5 Transmit Enable (TE): Bit 5 selects enabling or disabling of the start of transmit
operation.
Bit 5: TE
0
1
Notes: 1. Bit TDRE in SSR is fixed at 1.
Bit 4 Receive Enable (RE): Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4: RE
0
1
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
Bit 3 Multiprocessor Interrupt Enable (MPIE): Bit 3 selects enabling or disabling of the
multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is
selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid
when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3: MPIE
0
1
Note:
Rev. 6.00 Sep 12, 2006 page 298 of 526
REJ09B0326-0600
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
3. When bit TXD in PMR7 is set to 1. When bit TXD is cleared to 0, the TXD pin functions
2. In this state, serial data reception is started when a start bit is detected in asynchronous
* Receive data transfer from RSR to RDR, receive error detection, and setting of the
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings to decide the transmission format before setting bit TE to 1.
as an I/O port regardless of the TE bit setting.
cleared to 0, and retain their previous state.
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of
the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor
bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is
received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI
and ERI requests (when bits TIE and RIE in serial control register (SCR) are set to 1)
and setting of the RDRF, FER, and OER flags are enabled.
Description
Transmit operation disabled *
Transmit operation enabled *
Description
Receive operation disabled *
Receive operation enabled *
Description
Multiprocessor interrupt request disabled (normal receive operation)
Clearing condition:
When data is received in which the multiprocessor bit is set to 1
Multiprocessor interrupt request enabled *
2
1
2
1
(RXD pin is receive data pin)
(RXD pin is I/O port)
(TXD pin is transmit data pin) *
(TXD pin is transmit data pin) *
3
3
(initial value)
(initial value)
(initial value)