HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 333

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 10.12 SMR and SCR3 Settings and Clock Source Selection
SMR
Bit 7:
COM
0
1
0
1
1
Interrupts and Continuous Transmission/Reception: SCI3 can carry out continuous reception
using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13.
Table 10.13 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Bit 1:
CKE1
0
1
0
1
1
0
1
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
SCR3
Bit 0:
CKE0
0
1
0
0
0
1
1
1
Interrupt Request Conditions
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.7 (a).)
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1. If
bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.7 (b).)
When the last bit of the character in TSR
is transmitted, if bit TDRE is set to 1, bit
TEND is set to 1. If bit TEIE is set to 1 at
this time, TEI is enabled and an interrupt
is requested. (See figure 10.7 (c).)
Mode
Asynchronous
mode
Synchronous
mode
Reserved (Do not specify these combinations)
Internal
Clock
Source
External
Internal
External
Section 10 Serial Communication Interface
Rev. 6.00 Sep 12, 2006 page 311 of 526
SCK
I/O port (SCK
Outputs clock with same frequency as
bit rate
Inputs clock with frequency 16 times
bit rate
Outputs serial clock
Inputs serial clock
Transmit/Receive Clock
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
Notes
3
Pin Function
3
pin not used)
REJ09B0326-0600