HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 46

IC H8/3644 MCU FLASH 32K 64SDIP

HD64F3644PV

Manufacturer Part Number
HD64F3644PV
Description
IC H8/3644 MCU FLASH 32K 64SDIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644PV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644PV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
HD64F3644PV
Manufacturer:
RENESAS
Quantity:
25
Section 2 CPU
5. Absolute Address @aa:8 or @aa:16: The instruction specifies the absolute address of the
6. Immediate #xx:8 or #xx:16: The second byte (#xx:8) or the third and fourth bytes (#xx:16)
7. Program-Counter Relative @(d:8, PC): This mode is used in the Bcc and BSR
8. Memory Indirect @@aa:8: This mode can be used by the JMP and JSR instructions. The
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.3.2, Memory Data Formats, for further
information.
Rev. 6.00 Sep 12, 2006 page 24 of 526
REJ09B0326-0600
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
of the instruction code are used directly as the operand. Only MOV.W instructions can be used
with #xx:16.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address, and the PC
contents to be added are the start address of the next instruction, so that the possible branching
range is –126 to +128 bytes (–63 to +64 words) from the branch instruction. The displacement
should be an even number.
second byte of the instruction code specifies an 8-bit absolute address. This specifies an
operand in memory, and a branch is performed with the contents of this operand as the branch
address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector
area.
Register indirect with pre-decrement @–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.

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