HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 83

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the
WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows,
the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set
to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see section 9.6, Watchdog Timer.
3.2.3
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3
3.3.1
The interrupt sources include 12 external interrupts (IRQ
interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the
highest priority is processed.
The interrupts have the following features:
Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
IRQ
edge sensing.
3
to IRQ
Interrupt Immediately after Reset
Interrupts
Overview
0
and INT
7
to INT
0
can be set independently to either rising edge sensing or falling
3
to IRQ
Rev. 6.00 Sep 12, 2006 page 61 of 526
0
, INT
Section 3 Exception Handling
7
to INT
0
REJ09B0326-0600
) and 21 internal