HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 85

IC H8/3644 MCU FLASH 32K 64SDIP

HD64F3644PV

Manufacturer Part Number
HD64F3644PV
Description
IC H8/3644 MCU FLASH 32K 64SDIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644PV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644PV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
HD64F3644PV
Manufacturer:
RENESAS
Quantity:
25
3.3.2
Table 3.3 lists the registers that control interrupts.
Table 3.3
Name
Interrupt edge select register 1
Interrupt edge select register 2
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Note:
Interrupt Edge Select Register 1 (IEGR1)
IEGR1 is an 8-bit read/write register used to designate whether pins IRQ
edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.
Bit 7 Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified.
Bits 6 to 4 Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bit 3 IRQ
Bit 3: IEG3
0
1
Bit
Initial value
Read/Write
* Write is enabled only for writing of 0 to clear a flag.
Interrupt Control Registers
3
Interrupt Control Registers
Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ
Falling edge of IRQ
Rising edge of IRQ
Description
7
0
1
6
Abbreviation
IEGR1
IEGR2
IENR1
IENR2
IENR3
IRR1
IRR2
IRR3
3
3
pin input is detected
pin input is detected
1
5
4
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W *
R/W *
R/W *
Rev. 6.00 Sep 12, 2006 page 63 of 526
IEG3
R/W
3
0
Section 3 Exception Handling
Initial Value
H'70
H'00
H'10
H'00
H'00
H'10
H'00
H'00
IEG2
R/W
3
2
0
to IRQ
3
.
REJ09B0326-0600
0
IEG1
R/W
are set to rising
1
0
(initial value)
H'FFF2
H'FFF3
H'FFF4
H'FFF5
H'FFF6
H'FFF7
H'FFF8
H'FFF9
Address
IEG0
R/W
0
0

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