R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 227

MCU 24KB FLASH 256K ROM 144-LQFP

R5F61622N50FPV

Manufacturer Part Number
R5F61622N50FPV
Description
MCU 24KB FLASH 256K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61622N50FPV

Core Size
16/32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
H8SX
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b, 6x16b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
No. Of I/o's
74
Ram Memory Size
24KB
Cpu Speed
50MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61622N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(6)
Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area
5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that
the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in
SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an
external address space. For details, see section 3, MCU Operating Modes.
When area 5 external address space is accessed, the CS5 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in
SRAMCR. Table 8.12 shows the external interface of area 5.
Table 8.12 Area 5 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
Area 5
MPXE5 of MPXCR
0
0
1
1
Register Setting
Rev. 2.00 Sep. 16, 2009 Page 197 of 1036
BCSEL5 of SRAMCR
0
1
0
1
Section 8 Bus Controller (BSC)
REJ09B0414-0200

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