R5F61622N50FPV Renesas Electronics America, R5F61622N50FPV Datasheet - Page 242
R5F61622N50FPV
Manufacturer Part Number
R5F61622N50FPV
Description
MCU 24KB FLASH 256K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61622N50FPV
Core Size
16/32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
H8SX
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b, 6x16b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
No. Of I/o's
74
Ram Memory Size
24KB
Cpu Speed
50MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61622N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 Bus Controller (BSC)
8.6.6
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, LHWR, and LLWR.
Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle. Extension of the CS assertion period can
be set in area units. With the CS assertion extension period in write access, the data setup and hold
times are less stringent since the write data is output to the data bus.
Figure 8.22 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after
the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in
CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0).
Rev. 2.00 Sep. 16, 2009 Page 212 of 1036
REJ09B0414-0200
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