HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 388
HD64F2145BTE20
Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2145BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 13 Timer Connection
13.4.3
Measurement of 8-Bit Timer Divided Waveform Period
The timer connection facility, TMR_1, and the free-running timer (FRT) can be used to measure
the period of an IHI signal divided waveform. Since TMR_1 can be cleared by a rising edge of the
inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with
the IVI signal. This enables period measurement to be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR_1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The value to be used as the division factor is written in TCORA, and
the TMO output method is specified by the OS bits in TCSR.
Examples of TCR and TCSR settings in TMR_1, and TCR and TCSR settings in the FRT are
shown in table 13.6, and the timing chart for measurement of the IVI signal and IHI signal divided
waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform is given
by (ICRD(3) – ICRD(2))
resolution.
Rev. 3.00 Mar 21, 2006 page 332 of 788
REJ09B0300-0300
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