HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 161
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.1
The chip has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters—the CPU, DMA controller (DMAC), and data transfer controller (DTC).
6.1.1
The features of the bus controller are listed below.
• Manages external address space in area units
• Basic bus interface
• DRAM interface
• Burst ROM interface
⎯ In advanced mode, manages the external space as 8 areas of 2 Mbytes
⎯ Bus specifications can be set independently for each area
⎯ DRAM and burst ROM interfaces can be set
⎯ Chip select signals (CS
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ DRAM interface can be set for areas 2 to 5 (in advanced mode)
⎯ Row address/column address multiplexed output (8/9/10 bits)
⎯ 2-CAS access method
⎯ Burst operation (fast page mode)
⎯ TP cycle insertion to secure RAS precharging time
⎯ Selection of CAS-before-RAS refreshing or self-refreshing
⎯ Burst ROM interface can be set for area 0
⎯ Selection of 1- or 2-state burst access
Overview
Features
Section 6 Bus Controller
0
to CS
7
) can be output for areas 0 to 7
Rev.4.00 Sep. 07, 2007 Page 129 of 1210
REJ09B0245-0400
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