HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 222
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Rev.4.00 Sep. 07, 2007 Page 190 of 1210
REJ09B0245-0400
Address bus
CS (area A)
CS (area B)
RD
φ
Figure 6.33 Relationship between Chip Select (CS) and Read (RD)
Possibility of overlap between
CS (area B) and RD
T
(a) Idle cycle not inserted
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
T
2
(ICIS1 = 1 (initial value))
T
3
T
I
Bus cycle B
T
1
T
2
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