HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 285
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 285 of 1246
- Download datasheet (7Mb)
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
Set transfer source and
Set number of transfers
Single address mode
transfer destination
Read DMABCRL
Set DMABCRH
Set DMABCRL
Single address
mode setting
Set DMACR
addresses
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode is Specified)
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address/transfer
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTE bit to 1 to enable transfer.
• Clear the FAE bit to 0 to select short address
• Set the SAE bit to 1 to select single address
• Specify enabling or disabling of internal
destination address in MAR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the RPE bit to 0 to select sequential
• Specify the transfer direction with the DTDIR
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
mode.
mode.
interrupt clearing with the DTA bit.
decremented with the DTID bit.
mode.
bit.
DTF0.
interrupts with the DTIE bit.
Rev.4.00 Sep. 07, 2007 Page 253 of 1210
REJ09B0245-0400
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