HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 312

• Manufacturer Part Number: HD64F2338VFC25
• Description: MCU 3V 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2338VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ
pin is selected to 1.
Figure 7.32 shows an example of DREQ pin low level activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
Rev.4.00 Sep. 07, 2007 Page 280 of 1210
REJ09B0245-0400
Figure 7.32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[7]
release
Bus