HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 332
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number:
HD64F2338VFC25
Manufacturer:
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Quantity:
10 000
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Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER are not performed.
When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit.
Bit 7
CHNE
0
1
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
0
1
Bit 5—DTC Chain Transfer Select (CHNS): Specifies the chain transfer condition when CHNE
is 1.
Bit 7
CHNE
0
1
1
Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the chip and should always
be written with 0.
Rev.4.00 Sep. 07, 2007 Page 300 of 1210
REJ09B0245-0400
Description
End of DTC data transfer (activation waiting state)
DTC chain transfer (new register information is read, then data is transferred)
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bit 5
CHNS
—
0
1
Description
No chain transfer (DTC data transfer end, activation waiting state entered)
DTC chain transfer
Chain transfer only when transfer counter = 0
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