HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 415
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 415 of 1246
- Download datasheet (7Mb)
Port 8 Data Register (P8DR)
P8DR is a 7-bit readable/writable register that stores output data for the port 8 pins (P8
Bit 7 is reserved; it returns an undefined value if read, and cannot be modified.
P8DR is initialized to H'00 (bits 6 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port 8 Register (PORT8)
Note: * Determined by state of pins P8
PORT8 is a 7-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 8 pins (P8
Bit 7 is reserved; it returns an undefined value if read, and cannot be modified.
If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read. If a port 8
read is performed while P8DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT8 contents are determined by the pin states, as
P8DDR and P8DR are initialized. PORT8 retains its prior state in software standby mode.
Bit
Initial value : Undefined
R/W
Bit
Initial value : Undefined
R/W
:
:
:
:
—
—
—
—
7
7
P86DR
R/W
P86
— *
R
6
0
6
6
to P8
6
P85DR
to P8
R/W
P85
— *
0
R
) must always be performed on P8DR.
5
0
5
0
.
P84DR
R/W
P84
— *
R
0
4
4
Rev.4.00 Sep. 07, 2007 Page 383 of 1210
P83DR
R/W
P83
— *
R
3
0
3
P82DR
R/W
P82
— *
R
2
0
2
P81DR
REJ09B0245-0400
R/W
P81
— *
R
1
0
1
6
to P8
P80DR
R/W
P80
— *
R
0
0
0
0
).
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