HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 492
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Channel
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
Rev.4.00 Sep. 07, 2007 Page 460 of 1210
REJ09B0245-0400
3
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
Bit 7
IOD3
0
1
count clock, this setting is invalid and input capture is not generated.
setting is invalid and input capture/output compare is not generated.
Bit 6
IOD2
1
0
0
1
Bit 5
IOD1
1
0
1
1
*
0
0
Bit 4
IOD0 Description
0
1
0
1
0
1
0
1
0
1
*
*
TGR3D
is output
compare
register*
TGR3D
is input
capture
register *
2
2
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
Output disabled
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-
up/count-down *
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
(Initial value)
*: Don’t care
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