HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 587
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number:
HD64F2338VFC25
Manufacturer:
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10 000
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12.1
The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has
an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are
constantly compared with the TCNT value to detect compare match events. The 8-bit timer
module can thus be used for a variety of functions, including pulse output with an arbitrary duty
cycle.
12.1.1
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
• Selection of three ways to clear the counters
• Timer output control by a combination of two compare match signals
• Provision for cascading of two channels
• Three independent interrupts
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter)
The counters can be cleared on compare match A or B, or by an external reset signal
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
⎯ Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1
⎯ Channel 1 can be used to count channel 0 compare matches (compare match count mode)
Compare match A and B and overflow interrupts can be requested independently
Channel 0 compare match A signal can be used as an A/D converter conversion start trigger
As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting
module stop mode
for the lower 8 bits (16-bit count mode)
Overview
Features
Section 12 8-Bit Timers
Rev.4.00 Sep. 07, 2007 Page 555 of 1210
REJ09B0245-0400
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