HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 619
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other
registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for
RSTCSR.
13.3
13.3.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
This ensures that TCNT does not overflow while the system is operating normally. If TCNT
overflows without being rewritten because of a system crash or other error, the WDTOVF signal is
output. This is shown in figure 13.4. This WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip
internally is generated at the same time as the WDTOVF signal. The internal reset signal is output
for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Writing 0 to WOVF bit
Writing to RSTE bit
Operation
Operation in Watchdog Timer Mode
Address: H'FFBE
Address: H'FFBE
Figure 13.3 Writing to RSTCSR
15
15
H'A5
H'5A
Rev.4.00 Sep. 07, 2007 Page 587 of 1210
8 7
8 7
Write data
H'00
REJ09B0245-0400
0
0
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