HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 801
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 801 of 1246
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Table 19.12 Software Protection
Item
SWE bit protection
Block specification
protection
Emulation protection •
19.8.3
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during
• When a bus master other than the CPU (the DMAC or DTC) has control of the bus during
fetch)
programming/erasing
programming/erasing
Error Protection
Description
•
•
•
Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected state for all blocks.
(Execute in on-chip RAM or external memory.)
Erase protection can be set for individual
blocks by settings in erase block registers
1 and 2 (EBR1, EBR2).
Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Setting the RAMS bit to 1 in the RAM emulation
register (RAMER) places all blocks in the
program/erase-protected state.
Rev.4.00 Sep. 07, 2007 Page 769 of 1210
Program
Yes
—
Yes
REJ09B0245-0400
Functions
Erase
Yes
Yes
Yes
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