HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 837

• Manufacturer Part Number: HD64F2338VFC25
• Description: MCU 3V 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2338VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE
0
1
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.14.6 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 19.29. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit
Initial value :
R/W
Description
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
:
:
—
—
7
0
—
—
6
0
—
—
5
0
—
—
0
4
Rev.4.00 Sep. 07, 2007 Page 805 of 1210
RAMS
R/W
3
0
RAM2
R/W
2
0
REJ09B0245-0400
RAM1
R/W
1
0
(Initial value)
RAM0
R/W
0
0