MC68HC711E9CFNE3 Freescale Semiconductor, MC68HC711E9CFNE3 Datasheet - Page 35

• Manufacturer Part Number: MC68HC711E9CFNE3
• Description: IC MCU 3MHZ 12K OPT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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Addr.
Timer Output Compare 1 Register
Timer Output Compare 1 Register
Timer Output Compare 2 Register
Output Compare 1 Data Register
TImer Input Capture 2 Register
Timer Input Capture 1 Register
Timer Input Capture 1 Register
Timer Input Capture 2 Register
Timer Input Capture 3 Register
Timer Input Capture 3 Register
Timer Counter Register High
Timer Counter Register Low
Register Name
Figure 2-7. Register and Control Bit Assignments (Sheet 2 of 6)
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High (TOC1H)
High (TOC2H)
Low (TOC1L)
High (TIC1H)
High (TIC2H)
High (TIC3H)
Low (TIC1L)
Low (TIC2L)
Low (TIC3L)
(TCNTH)
(TCNTL)
(OC1D)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read: Bit 15
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
M68HC11E Family Data Sheet, Rev. 5.1
I = Indeterminate after reset
OC1D7
Bit 15
Bit 15
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
1
1
0
0
0
= Unimplemented
OC1D6
Bit 14
Bit 14
Bit 14
Bit 14
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
1
1
1
6
0
0
0
OC1D5
Bit 13
Bit 13
Bit 13
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
5
0
0
0
1
1
1
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
OC1D4
Bit 12
Bit 12
Bit 12
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
1
1
1
R
4
0
0
0
= Reserved
OC1D3
Bit 11
Bit 11
Bit 11
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
1
1
1
3
0
0
0
Bit 10
Bit 10
Bit 10
Bit 10
Bit 10
Bit 10
U = Unaffected
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
1
1
1
2
0
0
0
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
1
1
1
1
0
0
0
Memory Map
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0
0
1
1
1
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