MC68HC711E9CFNE3 Freescale Semiconductor, MC68HC711E9CFNE3 Datasheet - Page 95

• Manufacturer Part Number: MC68HC711E9CFNE3
• Description: IC MCU 3MHZ 12K OPT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6.2 Stop Mode
Executing the STOP instruction while the S bit in the CCR is equal to 0 places the MCU in stop mode. If
the S bit is not 0, the stop opcode is treated as a no-op (NOP). Stop mode offers minimum power
consumption because all clocks, including the crystal oscillator, are stopped while in this mode. To exit
stop and resume normal processing, a logic low level must be applied to one of the external interrupts
(IRQ or XIRQ) or to the RESET pin. A pending edge-triggered IRQ can also bring the CPU out of stop.
Because all clocks are stopped in this mode, all internal peripheral functions also stop. The data in the
internal RAM is retained as long as V
and are unchanged by stop. Therefore, when an interrupt comes to restart the system, the MCU resumes
processing as if there were no interruption. If reset is used to restart the system, a normal reset sequence
results in which all I/O pins and functions are also restored to their initial states.
To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must be clear (IRQ not
masked). The XIRQ pin can be used to wake up the MCU from stop regardless of the state of the X bit in
the CCR, although the recovery sequence depends on the state of the X bit. If X is set to 0 (XIRQ not
Freescale Semiconductor
VALID SCI REQUEST
RDRF = 1?
TDRE = 1?
IDLE = 1?
OR = 1?
TC = 1?
BEGIN
FLAG
N
N
N
N
N
NO
Figure 5-7. Interrupt Source Resolution Within SCI
Y
Y
Y
Y
Y
M68HC11E Family Data Sheet, Rev. 5.1
DD
power is maintained. The CPU state and I/O pin levels are static
ILIE = 1?
RIE = 1?
TIE = 1?
N
N
N
Y
Y
Y
TCIE = 1?
RE = 1?
RE = 1?
TE = 1?
N
N
N
N
VALID SCI REQUEST
Y
Y
Y
Y
Low-Power Operation
95