R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 272
![MCU 24KB FLASH 384K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 272 of 1070
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Section 8 Bus Controller (BSC)
(3)
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).
Figure 8.39 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM
device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Rev. 2.00 Sep. 16, 2009 Page 242 of 1036
REJ09B0414-0200
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
Read after Write
Figure 8.39 Example of Idle Cycle Operation (Read after Write)
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS2 = 0)
T
2
Output floating
time is long.
T
3
Bus cycle B
T
1
T
2
Data conflict
T
(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Bus cycle A
1
T
2
(b) Idle cycle inserted
T
3
T
Bus cycle B
i
T
1
T
2
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