R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 285
![MCU 24KB FLASH 384K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 285 of 1070
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8.14.2
Even if a bus request is received from a bus master with a higher priority over that of the bus
master that has taken control of the bus and is currently operating, the bus is not necessarily
transferred immediately. There are specific timings at which each bus master can release the bus.
(1)
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or
DMAC, the bus arbiter transfers the bus to the bus master that issued the request.
The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is
transferred synchronously with the clock.
Note, however, that the bus cannot be transferred in the following cases.
• The word or longword access is performed in some divisions.
• Stack handling is performed in multiple bus cycles.
• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS
• From the target read to write in the bit manipulation instructions or memory operation
(2)
The DTC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DTC accesses an external bus space, the DTC first takes control of the bus
from the internal bus arbiter and then requests a bus to the external bus arbiter.
Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus
master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the
higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the
CPU.
Note, however, that the bus cannot be transferred in the following cases.
instruction.
(In the block transfer instructions, the bus can be transferred in the write cycle and the
following transfer data read cycle.)
instructions.
(In an instruction that performs no write operation according to the instruction condition, up to
a cycle corresponding the write cycle)
CPU
DTC
Bus Transfer Timing
Rev. 2.00 Sep. 16, 2009 Page 255 of 1036
Section 8 Bus Controller (BSC)
REJ09B0414-0200
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