DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 211
DF2372VFQ34V
Manufacturer Part Number
DF2372VFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 211 of 1208
- Download datasheet (8Mb)
6.3.1
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
7
6
5
4
3
2
1
0
Note:
6.3.2
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
7
6
5
4
3
2
1
0
* In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Bit Name
Bit Name
Bus Width Control Register (ABWCR)
Access State Control Register (ASTCR)
to 0.
Initial Value *
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
1: Area n is designated as 3-state access space
Wait state insertion in area n access is
disabled
Wait state insertion in area n access is
enabled
Rev.7.00 Mar. 18, 2009 page 143 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
(n = 7 to 0)
(n = 7 to 0)
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