DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 224
DF2372VFQ34V
Manufacturer Part Number
DF2372VFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller (BSC)
6.3.8
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
15
14
13
Rev.7.00 Mar. 18, 2009 page 156 of 1136
REJ09B0109-0700
Bit Name
OEE
RAST
—
DRAM Control Register (DRAMCR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
OE Output Enable
The OE signal used when EDO page mode DRAM
is connected can be output from the (OE) pin. The
OE signal is common to all areas designated as
DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output from the (OE) pin. The
CKE signal is common to the continuous
synchronous DRAM space.
0: OE/CKE signal output disabled
1: OE/CKE signal output enabled
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal
is asserted from the start of the T
edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in T
1: RAS is asserted from start of T
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
(OE)/(CKE) pin can be used as I/O port
r
r
cycle (rising
cycle
r
cycle
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